Simulation and Synthesis

The two major purposes of HDLs are logic simulation and synthesis

• During simulation, inputs are applied to a module, and the outputs are checked to verify that the module operates correctly
• During synthesis, the textual description of a module is transformed into logic gates

Circuit descriptions in HDL resemble code in a programming language. But  the code is intended to represent hardware

IEEE-1364 / IEEE-1800

Verilog 2005 (IEEE Standard 1364-2005) consists of minor corrections, spec clarifications, and a few new language features

SystemVerilog is a superset of Verilog-2005, with many new features and capabilities to aid design-verification and design-modeling

System Verilog - History

• SystemVerilog is the industry's first unified hardware description and verification language
• Started with Superlog language to Accellera  in 2002
• Verification functionality (base on OpenVera language) came from Synopsys
• In 2005 SystemVerilog was adopted as IEEE Standard (1800-2005). The current version is 1800-2012

Verilog - History

1984: Verilog was developed by Gateway Design Automation as a proprietary language for logic simulation. 

 

1989: Gateway was acquired by Cadence

 

1990: Verilog was made an open standard under the control of Open Verilog International

 

1995: The language became an IEEE standard (IEEE STD 1364) and was updated in 2001 and 2005.

 

What is HDL?

Hardware Description Language

High Level Language

• To describe the circuits by syntax and sentences
• As oppose to circuit described by schematics
• Allows designers to model the concurrency of process found in hardware

Widely used HDLs

• Verilog – Similar to C
• SystemVerilog – Similar to C++
• VHDL – Similar to PASCAL

Beware! HDL are not like “typical” sequential languages.